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HD74CBT1G125
Single FET Bus Switch
REJ03D0815-0100 (Previous: ADE-205-645) Rev.1.00 Apr 07, 2006
Description
The HD74CBT1G125 features a single high-speed line switch. The switch is disabled when the output enable (OE) input is high.
Features
* * * * Minimal propagation delay through the switch. 5 switch connection between two ports. TTL-compatible input levels. Ultra low quiescent power. Ideally suited for notebook applications. * Ordering Information
Part Name Package Type Package Code (Previous code) PTSP0005ZC-A (CMPAK-5V) CM Package Abbreviation Taping Abbreviation (Quantity) E (3,000pcs / Reel)
HD74CBT1G125CME CMPAK-5pin
Outline and Article Indication
* HD74CBT1G125
Index band Marking
B
B
CMPAK-5
= Control code ( or blank)
Function Table
Input OE L H H: L: High level Low level Function A port = B port Disconnect
Rev.1.00 Apr 07, 2006 page 1 of 6
HD74CBT1G125
Pin Arrangement
OE
1
5
VCC
A
2
GND
3
4
B
(Top view)
Absolute Maximum Ratings
Item Supply voltage range Input voltage range *1 Input clamp current Continuous output current Continuous current through VCC or GND Maximum power dissipation *2 at Ta = 25C (in still air) Storage temperature Notes: Symbol VCC VI IIK IO ICC or IGND PT Tstg Ratings -0.5 to 7.0 -0.5 to 7.0 -50 128 100 200 -65 to 150 Unit V V mA mA mA mW C Conditions
VI < 0 VO = 0 to VCC
The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded even if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation was calculated using a junction temperature of 150C.
Recommended Operating Conditions
Item Symbol Min Supply voltage range VCC 4.0 Input voltage range VI 0 Output voltage range VI/O 0 Input transition rise or fall rate t / v 0 Operating free-air temperature Ta -40 Note: Unused or floating inputs must be held high or low. Max 5.5 5.5 5.5 5 85 Unit V V V ns / V C Conditions
VCC = 4.5 to 5.5 V
Rev.1.00 Apr 07, 2006 page 2 of 6
HD74CBT1G125
DC Electrical Characteristics
(Ta = -40 to 85C)
Item Clamp diode voltage Input voltage On-state switch resistance *2 Symbol VCC (V) VIK 4.5 VIH 4.0 to 5.5 VIL 4.0 to 5.5 RON 4.0 4.5 4.5 4.5 Input current Off-state leakage current Quiescent supply current Increase in ICC per input *3 IIN IOZ ICC ICC 0 to 5.5 5.5 5.5 5.5 Min 2.0 Typ 14 5 5 10
*1
Max -1.2 0.8 20 7 7 15 1.0 1.0 1.0 2.5
Unit V V
Test conditions IIN = -18 mA
One input at 3.4 V, other inputs at VCC or GND Notes: For condition shown as Min or Max use the appropriate values under recommended operating conditions. 1. All typical values are at VCC = 5 V (unless otherwise noted), Ta = 25C. 2. Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower voltage of the two (A or B) terminals. 3. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
A A A mA
VIN = 2.4 V, IIN = 15 mA Typ at VCC = 4.0 V VIN = 0 V, IIN = 64 mA VIN = 0 V, IIN = 30 mA VIN = 2.4 V, IIN = 15 mA VIN = 5.5 V or GND 0 A, B VCC VIN = VCC or GND, IO = 0 mA
Capacitance
(Ta = 25C)
Item Symbol VCC (V) Min Typ Max Unit Control input capacitance CIN 5.0 3 pF Input / output capacitance CI/O (OFF) 5.0 5 pF Note: This parameter is determined by device characterization is not production tested. Test conditions VIN = 0 or 3 V VO = 0 or 3 V, OE = VCC
Rev.1.00 Apr 07, 2006 page 3 of 6
HD74CBT1G125
Switching Characteristics
(Ta = -40 to 85C) VCC = 4.0 V
Item Propagation delay time *1 Enable time Disable time Symbol tPLH tPHL tZH tZL tHZ tLZ Min Max 0.35 5.5 4.5 4.5 Unit ns ns ns Test conditions CL = 50 pF RL = 500 CL = 50 pF RL = 500 CL = 50 pF RL = 500 FROM (Input) A or B OE OE TO (Output) B or A A or B A or B
VCC = 5.00.5 V
Item Propagation delay time *1 Enable time Disable time Note: Symbol tPLH tPHL tZH tZL tHZ tLZ Min 1.6 1.0 1.0 Max 0.25 4.9 4.2 4.8 Unit ns ns ns Test conditions CL = 50 pF RL = 500 CL = 50 pF RL = 500 CL = 50 pF RL = 500 FROM (Input) A or B OE OE TO (Output) B or A A or B A or B
1. The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
Test Circuit
See under table 500 S1 OPEN GND
*1
CL = 50 pF
500
Load circuit for outputs Symbol t PLH / tPHL t ZH / t HZ t ZL / t LZ S1 OPEN OPEN 7V
Note: 1. CL includes probe and jig capacitance.
Rev.1.00 Apr 07, 2006 page 4 of 6
HD74CBT1G125 Waveforms - 1
tr 90 % Input 10 % t PLH 1.5 V 90 % 1.5 V 10 % t PHL V OH Output 1.5 V 1.5 V V OL GND tf 3V
Waveforms - 2
tf 90 % Output Control 1.5 V 10 % t ZL 10 % t LZ 3.5 V Waveform - A 1.5 V V OL + 0.3 V t ZH t HZ V OH - 0.3 V 1.5 V GND Notes: 1. All input pulses are supplied by generators having the following characteristics : PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. 2. Waveform - A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform - B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement. V OL V OH tr 90 % 1.5 V GND 3V
Waveform - B
Rev.1.00 Apr 07, 2006 page 5 of 6
HD74CBT1G125
Package Dimensions
JEITA Package Code SC-88A RENESAS Code PTSP0005ZC-A Previous Code CMPAK-5 / CMPAK-5V MASS[Typ.] 0.006g
D e
A Q c
E
HE LP L
A xM
A S A b
L1
A3 e
Reference Symbol
Dimension in Millimeters
A2
A
yS b b1 c c1
A1 S e1
A A1 A2 A3 b b1 c c1 D E e HE L L1 LP x y b2 e1 l1 Q
Min 0.8 0 0.8 0.15 0.1 1.8 1.15 1.8 0.3 0.1 0.2
Nom
0.9 0.25 0.22 0.2 0.13 0.11 2.0 1.25 0.65 2.1
Max 1.1 0.1 1.0 0.3 0.15 2.2 1.35 2.4 0.7 0.5 0.6 0.05 0.05 0.35 0.9
l1
b2 A-A Section Pattern of terminal position areas
1.5 0.25
Rev.1.00 Apr 07, 2006 page 6 of 6
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